The invention relates to the fabrication of integrated circuit devices, and more particularly, to a shallow trench isolation (STI) dummy pattern and layout method using the same.
Continued semiconductor device performance improvements are achieved by miniaturization of device features, resulting in continued reduction of semiconductor device dimensions. Active devices are electrically isolated over the surface of a substrate by areas of field isolation in which STI is a major application. Surface planarity of areas of field isolation is frequently obtained by applying chemical mechanical polishing (CMP) of a deposited layer of field isolation oxide.
Using the STI approach for VLSI technology, deep trenches are typically formed in the substrate by reactive ion etching. The trenches are typically about 5-6 μm deep, about 2-3 μm wide and spaced about 2.5-3.5 μm apart from other trenches. ULSI technology requires trenches that are deeper and spaced closer together, posing new problems in field turn-on, punchthrough and gap-fill within the trenches and others.
STI areas can be formed using, for example, Buried Oxide (BOX) isolation for the shallow trenches. The method involves filling the trenches with a chemical vapor deposition (CVD) of silicon dioxide (SiO2) and then etching, or mechanically or chemically polishing the SiO2 to yield a planar surface.
Following formation of trenches in the surface of a substrate they are filled with a suitable dielectric material such as oxide, polysilicon or an organic polymeric material, for example polyimide. While the dielectric-filled trench isolation can provide effective dielectric isolation between devices, the fundamental disadvantage is that the resulting structure tends to be non-planar, mainly due to the difference in the amount required to fill multiple closely spaced trenches and dielectric deposited on the surface of the substrate. This effect is further aggravated by steps of baking and curing applied to the deposited dielectric to cure the dielectric and evaporate solvents. Further problems can be caused in this respect by significant difference in device density across the chip. Poor planarity across the surface of the trenches leads to further problems in creating interconnect patterns and in depositing overlying layers of insulation and metallization.
Another problem associated with the formation of STI areas is that if the silicon oxide is etched or polished to the surface of the silicon substrate, dishing occurs in the surface of the silicon oxide, resulting in a concave surface of the STI areas, resulting recesses in the field oxide at the edge of the device areas. When gate electrodes are formed for CMOS devices, the gate electrodes extend over the device area edge, causing undesirable lower and variable threshold voltage when the devices are completed. It is therefore desirable to form isolation areas extending higher than the substrate surface to avoid such problems while reducing manufacturing costs.
U.S. Pat. No. 6,327,695 B1 (Bothra et al.) discloses a chip design method including STI and active area (AA) using dummy poly lines to reduce capacitance.
U.S. Pat. No. 6,020,616 (Bothra et al.) reveals a chip design method including STI and AA using dummy poly lines and dummy Active Areas.
U.S. Pat. No. 6,010,939 (Bothra), U.S. Pat. No. 6,335,560 B1 (Takeuchi) and U.S. Pat. No. 5,902,752 (Sun et al.) are related patents using dummy structures.